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参数资料
| 型号： | 477R-05I |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 74.175 MHz, VIDEO CLOCK GENERATOR, PDSO28 |
| 封装： | 0.150 INCH, SSOP-28 |
| 文件页数： | 4/8页 |
| 文件大小： | 192K |
| 代理商： | 477R-05I |
ICS477-05
QUAD PLL WITH VCXO FOR HDTV
VCXO AND SYNTHESIZER
IDT / ICS QUAD PLL WITH VCXO FOR HDTV
4
ICS477-05
REV H 062404
considered to reduce stray capacitance. (Alternately,
the crystal may be re-specified to a higher load
capacitance. Contact ICS for details.) If the centering
error is more than 25 ppm positive, add identical fixed
centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by:
External Capacitor =
2 x (centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied by
your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the
measurement to verify that the remaining error is
acceptably low (typically less than ±25 ppm).
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pins as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33
series termination resistor
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS477-05. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS477-05. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
7 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature (commercial)
0 to +70
° C
Ambient Operating Temperature (industrial)
-40 to +85
° C
Storage Temperature
-65 to +150
° C
Junction Temperature
125
° C
Soldering Temperature
260
° C
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 477R-05ILF | 功能描述:时钟发生器及支持产品 QUAD PLL WITH VCXO FOR HDTV RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| 477R-05ILFT | 功能描述:时钟发生器及支持产品 QUAD PLL WITH VCXO FOR HDTV RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| 477R-05LFT | 功能描述:时钟发生器及支持产品 QUAD PLL WITH VCXO FOR HDTV RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| 477RLS010M | 制造商:ILLINOISCAPACITOR 制造商全称:Illinois Capacitor, Inc. 功能描述:+85°C Low Leakage Radial Lead Aluminum Electrolytic Capacitors |
| 477RLS016M | 制造商:Illinois Capacitor Inc 功能描述:470uF 16WV +-20% *NO PB* |
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