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参数资料
| 型号： | 4450HA/3-K |
| 厂商： | EXAR CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROPROCESSOR, PBGA324 |
| 封装： | HSBGA-324 |
| 文件页数： | 47/92页 |
| 文件大小： | 780K |
| 代理商： | 4450HA/3-K |
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4450 – Data Sheet, DS-0131-06
Page 51
Hifn Confidential
6.2.4.4
GMAC SERDES/SGMII Pin Descriptions (Host/Network)
Table 6-13 contains the pin descriptions for the SERDES and SGMII host and network
interface ports when configured in PHY/MAC mode.
6.3 RMII Interface (Optional Control Interface)
Table 6-14 contains three columns for the signal name and pin mappings of the 100Mb
RMII Ethernet port. The leftmost column contains the 4450 pin name, and the next two
columns contain the functional signal name, based on whether the RMII port functions as a
MAC or a PHY device. Table 6-14 maps the 4450 pin names to the signal functions
depending on the settings of the RMII_PHY_MODE strap. There are two possibilities for the
control port, as indicated in Table 6-6.
Please note in Table 6-14 that the directions of the data and control signals associated with
the terms “receive” and “transmit” depend on whether the port is a MAC or a PHY. For
example, “receive” relates to data and control signals that are outputs on the PHY and
inputs on the MAC. And “transmit” relates to data and control signals that are inputs on the
PHY and outputs on the MAC.
The supply signal RMII_VDD is assigned to ball number U13 as 3.3V Vdde.
Table 6-13. 4450 SERDES/ SGMII pin descriptions - PHY/MAC mode
Pin Name
SERDES\SGMII
(MAC) Signal
I/O
SERDES\SGMII
(PHY) Signal
I/O
Description
refclk_p
in
refclk_p
in
reference clock input (positive),
requires pulldown resistors if
unused
refclk_n
in
refclk_n
in
reference clock input (negative),
requires pulldown resistors if
unused
xx_bus1_p
xx_rxd_p
in
xx_txd_p
in
data input (positive)
xx_bus1_n
xx_rxd_n
in
xx_txd_n
in
data input (negative)
xx_bus0_p
xx_txd_p
out
xx_rxd_p
out
data output (positive)
xx_bus0_n
xx_txd_n
out
xx_rxd_n
out
data output (negative)
Note
xx = n0, n1, h0 or h1
Table 6-14. 4450 RMII modes pin mappings
Pin Name
MAC-MII
PHY-MII
RMII Signal
I/O
RMII Signal
I/O
rmii_ref_clk
out
rmii_ref_clk
in
rmii_bus1[2]
rmii_crs_rdv
in
rmii_txen
in
rmii_bus1[1:0]
rmii_rxd[1:0]
in
rmii_txd[1:0]
in
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