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参数资料
| 型号： | 4302-52 |
| 厂商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分类： | 衰减器 |
| 英文描述： | 50 Ohm RF Digital Attenuator 6-bit, 31.5 dB, DC-4.0 GHZ |
| 中文描述： | 0 MHz - 4000 MHz RF/MICROWAVE VARIABLE ATTENUATOR, 1.75 dB INSERTION LOSS-MAX |
| 封装： | 4 X 4 MM, GREEN, QFN-20 |
| 文件页数： | 9/11页 |
| 文件大小： | 469K |
| 代理商： | 4302-52 |
Product Specification
PE4302
Page 7 of 11
Document No. 70-0056-04
│ www.psemi.com
2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE4302 Digital Step Attenuator.
J9 is used in conjunction with the supplied DC
cable to supply VDD, GND, and –VDD. If use of
the internal negative voltage generator is desired,
then connect –VDD (Black banana plug) to
ground. If an external –VDD is desired, then apply
-3V.
J1 should be connected to the parallel port of a
PC with the supplied ribbon cable. The evaluation
software is written to operate the DSA in serial
mode, so Switch 7 (P/S) on the DIP switch SW1
should be ON with all other switches off. Using the
software, enable or disable each attenuation
setting to the desired combined attenuation. The
software automatically programs the DSA each
time an attenuation state is enabled or disabled.
To evaluate the Power Up options, first disconnect
the parallel ribbon cable from the evaluation
board. The parallel cable must be removed to
prevent the PC parallel port from biasing the
control pins.
During power up with P/S=1 high and LE=0 or P/
S=0 low and LE=1, the default power-up signal
attenuation is set to the value present on the six
control bits on the six parallel data inputs (C0.5 to
C16). This allows any one of the 64 attenuation
settings to be specified as the power-up state.
During power up with P/S=0 high and LE=0, the
control bits are automatically set to one of four
possible values presented through the PUP
interface. These four values are selected by the
two power-up control bits, PUP1 and PUP2, as
shown in the Table 6.
Resistor on Pin 1 & 3
A 10 k
resistor on the inputs to Pin 1 & 3 (Figure
16) will eliminate package resonance between the
RF input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
Figure 15. Evaluation Board Layout
Figure 16. Evaluation Board Schematic
Z=50 Ohm
PUP2
J5
SMA
1
C2
C16
CLK
100 pF
DATA
C4
C0.5
10k
C8
Z=50 Ohm
PUP1
PS
C1
VDD
U1
MLPQ4X4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
C16
RFin
DATA
CLK
LE
VD
D
PU
P1
PU
P2
VD
D
_D
GN
D
GND
Vss/GND
PS
RFout
C8
C4
C2
GN
D
C1
C5
LE
J4
SMA
1
Note: Resistors on pins 1 and 3 are required to avoid package
resonance and meet error specifications over frequency.
Peregrine Specification 101/0112
Peregrine Specification 102/0144
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