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参数资料
| 型号： | 12C887 |
| 英文描述： | Test Prod Wire; Conductor Size AWG:18; No. Strands x Strand Size:65 x 36; Jacket Color:Black; Conductor Material:Copper; Jacket Material:Rubber; Leaded Process Compatible:Yes; Number of Conductors:1 RoHS Compliant: Yes |
| 中文描述： | 实时时钟 |
| 文件页数： | 2/19页 |
| 文件大小： | 193K |
| 代理商： | 12C887 |
DS12C887
10 of 19
CENTURY REGISTER
The century register at location 32h, is a BCD register designed to automatically load the BCD value 20
as the year register changes from 99 to 00. The MSB of this register will not be affected when the load of
20 occurs and will remain at the value written by the user.
NONVOLATILE RAM
The 113 general purpose nonvolatile RAM bytes are not dedicated to any special function within the
DS12C887. They can be used by the processor program as nonvolatile memory and are fully available
during the update cycle.
INTERRUPTS
The RTC plus RAM includes three separate, fully automatic sources of interrupt for a processor. The
alarm interrupt can be programmed to occur at rates from once per second to once per day. The periodic
interrupt can be selected for rates from 500ms to 122
s. The update-ended interrupt can be used to
indicate to the program that an update cycle is complete. Each of these independent interrupt conditions is
described in greater detail in other sections of this text.
The processor program can select which interrupts, if any, are going to be used. Three bits in Register B
enable the interrupts. Writing a logic 1 to an interrupt-enable bit permits that interrupt to be initiated
when the event occurs. A zero in an interrupt-enable bit prohibits the IRQ pin from being asserted from
that interrupt condition. If an interrupt flag is already set when an interrupt is enabled, IRQ is
immediately set at an active level, although the interrupt initiating the event may have occurred much
earlier. As a result, there are cases where the program should clear such earlier initiated interrupts before
first enabling new interrupts.
When an interrupt event occurs, the relating flag bit is set to logic 1 in Register C. These flag bits are set
independent of the state of the corresponding enable bit in Register B. The flag bit can be used in a
polling mode without enabling the corresponding enable bits. The interrupt flag bit is a status bit which
software can interrogate as necessary. When a flag is set, an indication is given to software that an
interrupt event has occurred since the flag bit was last read; however, care should be taken when using the
flag bits as they are cleared each time Register C is read. Double latching is included with Register C so
that bits which are set remain stable throughout the read cycle. All bits which are set (high) are cleared
when read and new interrupts which are pending during the read cycle are held until after the cycle is
completed. One, two, or three bits can be set when reading Register C. Each utilized flag bit should be
examined when read to ensure that no interrupts are lost.
The second flag bit usage method is with fully enabled interrupts. When an interrupt flag bit is set and the
corresponding interrupt enable bit is also set, the IRQ pin is asserted low. IRQ is asserted as long as at
least one of the three interrupt sources has its flag and enable bits both set. The IRQF bit in Register C is
a one whenever the IRQ pin is being driven low. Determination that the RTC initiated an interrupt is
accomplished by reading Register C. A logic one in bit 7 (IRQF bit) indicates that one or more interrupts
have been initiated by the DS12C887. The act of reading Register C clears all active flag bits and the
IRQF bit.
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